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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_rxcounters.v] - Rev 365

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Rev	Log message	Author	Age	Path
354	Whitespace cleanup	olof	4955d 01h	/ethmac/trunk/rtl/verilog/eth_rxcounters.v
353	Inherit fixes for bit width of constants from ORPSoC	olof	4957d 03h	/ethmac/trunk/rtl/verilog/eth_rxcounters.v
352	Removed delayed assignments from rtl code	olof	4961d 08h	/ethmac/trunk/rtl/verilog/eth_rxcounters.v
346	Updated project location	olof	4972d 01h	/ethmac/trunk/rtl/verilog/eth_rxcounters.v
338		root	5776d 04h	/ethmac/trunk/rtl/verilog/eth_rxcounters.v
335	New directory structure.	root	5833d 09h	/ethmac/trunk/rtl/verilog/eth_rxcounters.v
326	Delayed CRC fixed.	igorm	7310d 08h	/ethmac/trunk/rtl/verilog/eth_rxcounters.v
57	Format of the file changed a bit.	mohor	8412d 08h	/ethmac/trunk/rtl/verilog/eth_rxcounters.v
52	Modified for Address Checking, addition of eth_addrcheck.v	billditt	8412d 23h	/ethmac/trunk/rtl/verilog/eth_rxcounters.v
37	Link in the header changed.	mohor	8435d 08h	/ethmac/trunk/rtl/verilog/eth_rxcounters.v
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8531d 10h	/ethmac/trunk/rtl/verilog/eth_rxcounters.v
15	A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). Include files fixed to contain no path. File names and module names changed ta have a eth_ prologue in the name. File eth_timescale.v is used to define timescale All pin names on the top module are changed to contain _I, _O or _OE at the end. Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O and Mdo_OE. The bidirectional signal must be created on the top level. This is done due to the ASIC tools.	mohor	8605d 04h	/ethmac/trunk/rtl/verilog/eth_rxcounters.v

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