URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_shiftreg.v] - Rev 345

Rev	Log message	Author	Age	Path
338		root	5666d 13h	/ethmac/trunk/rtl/verilog/eth_shiftreg.v
335	New directory structure.	root	5723d 18h	/ethmac/trunk/rtl/verilog/eth_shiftreg.v
332	Case statement improved for synthesys.	igorm	7185d 14h	/ethmac/trunk/rtl/verilog/eth_shiftreg.v
131	LinkFail signal was not latching appropriate bit.	mohor	8122d 10h	/ethmac/trunk/rtl/verilog/eth_shiftreg.v
84	LinkFail signal was not latching appropriate bit.	mohor	8287d 07h	/ethmac/trunk/rtl/verilog/eth_shiftreg.v
37	Link in the header changed.	mohor	8325d 18h	/ethmac/trunk/rtl/verilog/eth_shiftreg.v
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8421d 20h	/ethmac/trunk/rtl/verilog/eth_shiftreg.v
15	A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). Include files fixed to contain no path. File names and module names changed ta have a eth_ prologue in the name. File eth_timescale.v is used to define timescale All pin names on the top module are changed to contain _I, _O or _OE at the end. Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O and Mdo_OE. The bidirectional signal must be created on the top level. This is done due to the ASIC tools.	mohor	8495d 14h	/ethmac/trunk/rtl/verilog/eth_shiftreg.v