URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_spram_256x32.v] - Rev 340

Rev	Log message	Author	Age	Path
338		root	5689d 12h	/ethmac/trunk/rtl/verilog/eth_spram_256x32.v
335	New directory structure.	root	5746d 18h	/ethmac/trunk/rtl/verilog/eth_spram_256x32.v
330	Warning fixes.	igorm	7223d 15h	/ethmac/trunk/rtl/verilog/eth_spram_256x32.v
312	Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16.	tadejm	7667d 15h	/ethmac/trunk/rtl/verilog/eth_spram_256x32.v
306	Lapsus fixed (!we -> ~we).	simons	7668d 13h	/ethmac/trunk/rtl/verilog/eth_spram_256x32.v
304	WISHBONE slave changed and tested from only 32-bit accesss to byte access.	tadejm	7690d 09h	/ethmac/trunk/rtl/verilog/eth_spram_256x32.v
302	mbist signals updated according to newest convention	markom	7716d 20h	/ethmac/trunk/rtl/verilog/eth_spram_256x32.v
297	Artisan ram instance added.	simons	7780d 11h	/ethmac/trunk/rtl/verilog/eth_spram_256x32.v
227	Changed BIST scan signals.	tadejm	8080d 11h	/ethmac/trunk/rtl/verilog/eth_spram_256x32.v
210	BIST added.	mohor	8088d 11h	/ethmac/trunk/rtl/verilog/eth_spram_256x32.v
204	ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).	mohor	8105d 09h	/ethmac/trunk/rtl/verilog/eth_spram_256x32.v
122	ethernet spram added. So far a generic ram and xilinx RAMB4 are used.	mohor	8167d 11h	/ethmac/trunk/rtl/verilog/eth_spram_256x32.v