OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_spram_256x32.v] - Rev 355

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
354 Whitespace cleanup olof 4862d 11h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
352 Removed delayed assignments from rtl code olof 4868d 19h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
346 Updated project location olof 4879d 11h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
338 root 5683d 14h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
335 New directory structure. root 5740d 19h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
330 Warning fixes. igorm 7217d 16h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
312 Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. tadejm 7661d 16h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
306 Lapsus fixed (!we -> ~we). simons 7662d 14h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 7684d 11h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
302 mbist signals updated according to newest convention markom 7710d 21h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
297 Artisan ram instance added. simons 7774d 12h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
227 Changed BIST scan signals. tadejm 8074d 12h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
210 BIST added. mohor 8082d 12h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 8099d 11h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 8161d 12h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.