OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_spram_256x32.v] - Rev 358

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4698d 23h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4698d 23h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4699d 01h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
354 Whitespace cleanup olof 4699d 02h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
352 Removed delayed assignments from rtl code olof 4705d 10h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
346 Updated project location olof 4716d 02h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
338 root 5520d 05h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
335 New directory structure. root 5577d 10h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
330 Warning fixes. igorm 7054d 07h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
312 Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. tadejm 7498d 07h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
306 Lapsus fixed (!we -> ~we). simons 7499d 05h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 7521d 02h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
302 mbist signals updated according to newest convention markom 7547d 12h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
297 Artisan ram instance added. simons 7611d 03h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
227 Changed BIST scan signals. tadejm 7911d 03h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
210 BIST added. mohor 7919d 04h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7936d 02h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 7998d 03h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.