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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_txethmac.v] - Rev 340

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Rev	Log message	Author	Age	Path
338		root	5687d 09h	/ethmac/trunk/rtl/verilog/eth_txethmac.v
335	New directory structure.	root	5744d 14h	/ethmac/trunk/rtl/verilog/eth_txethmac.v
328	Delayed CRC fixed.	igorm	7221d 13h	/ethmac/trunk/rtl/verilog/eth_txethmac.v
277	When padding was enabled and crc disabled, frame was not ended correctly.	mohor	7974d 11h	/ethmac/trunk/rtl/verilog/eth_txethmac.v
79	RetryCntLatched was unused and removed from design	mohor	8312d 08h	/ethmac/trunk/rtl/verilog/eth_txethmac.v
72	Retry is not activated when a Tx Underrun occured	mohor	8316d 11h	/ethmac/trunk/rtl/verilog/eth_txethmac.v
43	Tx status is written back to the BD.	mohor	8327d 15h	/ethmac/trunk/rtl/verilog/eth_txethmac.v
37	Link in the header changed.	mohor	8346d 14h	/ethmac/trunk/rtl/verilog/eth_txethmac.v
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8442d 15h	/ethmac/trunk/rtl/verilog/eth_txethmac.v
18	Few little NCSIM warnings fixed.	mohor	8480d 10h	/ethmac/trunk/rtl/verilog/eth_txethmac.v
15	A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). Include files fixed to contain no path. File names and module names changed ta have a eth_ prologue in the name. File eth_timescale.v is used to define timescale All pin names on the top module are changed to contain _I, _O or _OE at the end. Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O and Mdo_OE. The bidirectional signal must be created on the top level. This is done due to the ASIC tools.	mohor	8516d 09h	/ethmac/trunk/rtl/verilog/eth_txethmac.v

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