OpenCores

URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_txethmac.v] - Rev 355

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Rev	Log message	Author	Age	Path
353	Inherit fixes for bit width of constants from ORPSoC	olof	4847d 13h	/ethmac/trunk/rtl/verilog/eth_txethmac.v
352	Removed delayed assignments from rtl code	olof	4851d 19h	/ethmac/trunk/rtl/verilog/eth_txethmac.v
349	Make all parameters configurable from top level	olof	4861d 10h	/ethmac/trunk/rtl/verilog/eth_txethmac.v
346	Updated project location	olof	4862d 12h	/ethmac/trunk/rtl/verilog/eth_txethmac.v
338		root	5666d 14h	/ethmac/trunk/rtl/verilog/eth_txethmac.v
335	New directory structure.	root	5723d 19h	/ethmac/trunk/rtl/verilog/eth_txethmac.v
328	Delayed CRC fixed.	igorm	7200d 18h	/ethmac/trunk/rtl/verilog/eth_txethmac.v
277	When padding was enabled and crc disabled, frame was not ended correctly.	mohor	7953d 16h	/ethmac/trunk/rtl/verilog/eth_txethmac.v
79	RetryCntLatched was unused and removed from design	mohor	8291d 13h	/ethmac/trunk/rtl/verilog/eth_txethmac.v
72	Retry is not activated when a Tx Underrun occured	mohor	8295d 16h	/ethmac/trunk/rtl/verilog/eth_txethmac.v
43	Tx status is written back to the BD.	mohor	8306d 20h	/ethmac/trunk/rtl/verilog/eth_txethmac.v
37	Link in the header changed.	mohor	8325d 19h	/ethmac/trunk/rtl/verilog/eth_txethmac.v
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8421d 21h	/ethmac/trunk/rtl/verilog/eth_txethmac.v
18	Few little NCSIM warnings fixed.	mohor	8459d 15h	/ethmac/trunk/rtl/verilog/eth_txethmac.v
15	A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). Include files fixed to contain no path. File names and module names changed ta have a eth_ prologue in the name. File eth_timescale.v is used to define timescale All pin names on the top module are changed to contain _I, _O or _OE at the end. Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O and Mdo_OE. The bidirectional signal must be created on the top level. This is done due to the ASIC tools.	mohor	8495d 15h	/ethmac/trunk/rtl/verilog/eth_txethmac.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.