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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [ethmac_defines.v] - Rev 367

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Rev	Log message	Author	Age	Path
367	Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored	olof	4730d 10h	/ethmac/trunk/rtl/verilog/ethmac_defines.v
360	Added partial implementation of the debug register from ORPSoC	olof	4857d 19h	/ethmac/trunk/rtl/verilog/ethmac_defines.v
356	Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure	olof	4861d 13h	/ethmac/trunk/rtl/verilog/ethmac_defines.v
351	Turn defines into parameters in eth_cop	olof	4876d 11h	/ethmac/trunk/rtl/verilog/eth_defines.v
350	Turn M[1-2]_ADDRESSED_S[1-2] defines into wires	olof	4876d 12h	/ethmac/trunk/rtl/verilog/eth_defines.v
346	Updated project location	olof	4878d 14h	/ethmac/trunk/rtl/verilog/eth_defines.v
338		root	5682d 17h	/ethmac/trunk/rtl/verilog/eth_defines.v
335	New directory structure.	root	5739d 22h	/ethmac/trunk/rtl/verilog/eth_defines.v
330	Warning fixes.	igorm	7216d 19h	/ethmac/trunk/rtl/verilog/eth_defines.v
304	WISHBONE slave changed and tested from only 32-bit accesss to byte access.	tadejm	7683d 14h	/ethmac/trunk/rtl/verilog/eth_defines.v
302	mbist signals updated according to newest convention	markom	7710d 00h	/ethmac/trunk/rtl/verilog/eth_defines.v
297	Artisan ram instance added.	simons	7773d 15h	/ethmac/trunk/rtl/verilog/eth_defines.v
286	Define file in eth_cop.v is changed to eth_defines.v. Some defines were moved from tb_eth_defines.v to eth_defines.v.	mohor	7835d 20h	/ethmac/trunk/rtl/verilog/eth_defines.v
253	r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.	mohor	8041d 14h	/ethmac/trunk/rtl/verilog/eth_defines.v
246	Since r_Rst bit is not used any more, default value is changed to 0xa000.	mohor	8045d 17h	/ethmac/trunk/rtl/verilog/eth_defines.v
238	Defines fixed to use generic RAM by default.	mohor	8059d 14h	/ethmac/trunk/rtl/verilog/eth_defines.v
232	fpga define added.	mohor	8067d 13h	/ethmac/trunk/rtl/verilog/eth_defines.v
213	Defines changed to have ETH_ prolog. ETH_WISHBONE_B# define added.	mohor	8081d 15h	/ethmac/trunk/rtl/verilog/eth_defines.v
211	Bist added.	mohor	8081d 15h	/ethmac/trunk/rtl/verilog/eth_defines.v
203	Virtual Silicon RAM might be used in the ASIC implementation of the ethernet core.	mohor	8098d 14h	/ethmac/trunk/rtl/verilog/eth_defines.v

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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [ethmac_defines.v] - Rev 367

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