URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [ethmac_defines.v] - Rev 357

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
356	Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure	olof	4865d 10h	/ethmac/trunk/rtl/verilog/ethmac_defines.v
351	Turn defines into parameters in eth_cop	olof	4880d 08h	/ethmac/trunk/rtl/verilog/eth_defines.v
350	Turn M[1-2]_ADDRESSED_S[1-2] defines into wires	olof	4880d 09h	/ethmac/trunk/rtl/verilog/eth_defines.v
346	Updated project location	olof	4882d 11h	/ethmac/trunk/rtl/verilog/eth_defines.v
338		root	5686d 14h	/ethmac/trunk/rtl/verilog/eth_defines.v
335	New directory structure.	root	5743d 19h	/ethmac/trunk/rtl/verilog/eth_defines.v
330	Warning fixes.	igorm	7220d 16h	/ethmac/trunk/rtl/verilog/eth_defines.v
304	WISHBONE slave changed and tested from only 32-bit accesss to byte access.	tadejm	7687d 10h	/ethmac/trunk/rtl/verilog/eth_defines.v
302	mbist signals updated according to newest convention	markom	7713d 21h	/ethmac/trunk/rtl/verilog/eth_defines.v
297	Artisan ram instance added.	simons	7777d 12h	/ethmac/trunk/rtl/verilog/eth_defines.v
286	Define file in eth_cop.v is changed to eth_defines.v. Some defines were moved from tb_eth_defines.v to eth_defines.v.	mohor	7839d 17h	/ethmac/trunk/rtl/verilog/eth_defines.v
253	r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.	mohor	8045d 11h	/ethmac/trunk/rtl/verilog/eth_defines.v
246	Since r_Rst bit is not used any more, default value is changed to 0xa000.	mohor	8049d 14h	/ethmac/trunk/rtl/verilog/eth_defines.v
238	Defines fixed to use generic RAM by default.	mohor	8063d 11h	/ethmac/trunk/rtl/verilog/eth_defines.v
232	fpga define added.	mohor	8071d 10h	/ethmac/trunk/rtl/verilog/eth_defines.v
213	Defines changed to have ETH_ prolog. ETH_WISHBONE_B# define added.	mohor	8085d 12h	/ethmac/trunk/rtl/verilog/eth_defines.v
211	Bist added.	mohor	8085d 12h	/ethmac/trunk/rtl/verilog/eth_defines.v
203	Virtual Silicon RAM might be used in the ASIC implementation of the ethernet core.	mohor	8102d 10h	/ethmac/trunk/rtl/verilog/eth_defines.v
145	Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL).	mohor	8121d 10h	/ethmac/trunk/rtl/verilog/eth_defines.v
137	Defines for register width added. mii_rst signal in MIIMODER register changed.	mohor	8140d 07h	/ethmac/trunk/rtl/verilog/eth_defines.v

1 2 Next >

Show All

Browse

Tools

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [ethmac_defines.v] - Rev 357

Filtering Options