URL https://opencores.org/ocsvn/ethmac10g/ethmac10g/trunk

Subversion Repositories ethmac10g

[/] [ethmac10g/] [trunk/] [rtl/] [verilog/] [rx_engine/] [rxDataPath.v] - Rev 72

Rev	Log message	Author	Age	Path
72	New directory structure.	root	5666d 17h	/ethmac10g/trunk/rtl/verilog/rx_engine/rxDataPath.v
71	Replay xilinx fifo with private fifo	fisher5090	6000d 14h	/ethmac10g/trunk/rtl/verilog/rx_engine/rxDataPath.v
69	no message	fisher5090	6664d 08h	/ethmac10g/trunk/rtl/verilog/rx_engine/rxDataPath.v
64	no message	fisher5090	6667d 19h	/ethmac10g/trunk/rtl/verilog/rx_engine/rxDataPath.v
63	remove pad function added, using xilinx vp20 -6 as target FPGA, passes post place and route simulation	fisher5090	6667d 19h	/ethmac10g/trunk/rtl/verilog/rx_engine/rxDataPath.v
57	both inband fcs and no inband fcs are OK	fisher5090	6668d 10h	/ethmac10g/trunk/rtl/verilog/rx_engine/rxDataPath.v
52	modified the rx_good_frame and rx_bad_frame timing sequence	fisher5090	6669d 07h	/ethmac10g/trunk/rtl/verilog/rx_engine/rxDataPath.v
39	first version	fisher5090	6680d 08h	/ethmac10g/trunk/rtl/verilog/rx_engine/rxDataPath.v