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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [fpdivr16.v] - Rev 34

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34 - add pipeline stage in divider robfinch 1524d 05h /ft816float/trunk/rtl/verilog2/fpdivr16.v
30 - move load signal to bottom robfinch 1792d 20h /ft816float/trunk/rtl/verilog2/fpdivr16.v
29 - refactor with FPWID and EXTRA_BITS
- Nan propagation
robfinch 1793d 04h /ft816float/trunk/rtl/verilog2/fpdivr16.v

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