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[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [GECKO3COM.ipf] - Rev 34

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22 a lot of work is done for the GECKO3COM_simple IP core. datapath and fsm is designed and implemente,
top level is implemented. needs still some tweks but time to make a backup!

the simple ip core will be tested together with the GECKO3COM_simple_test.		 nussgipfel 5394d 00h /gecko3/trunk/GECKO3COM/gecko3com-ip/core/GECKO3COM.ipf
18 I achieved now stable OUT transfers (from the PC to the FPGA) with working throtling (when the FPGA consumes data slower than the host delivers).
The basics needed for this are implemented in the FPGA like handshaking with the FX2 and clock domain transistion from the Interface clock to the user defined system clock.

in the gpif_com_test.vhd is a message rom, containing a prepared answer message to generate an IN transfer. this is needed for the next step.		 nussgipfel 5421d 03h /gecko3/trunk/GECKO3COM/gecko3com-ip/core/GECKO3COM.ipf
14 reorganising and renaming the stuff in these project.

the core will get the name "GECKO3COM_" followed by the type "simple", "plb" or "opb"
to follow the naming in the GECKO3 wiki and to show the IP core interface.

duplicated fifo corecenerator files are merged together including a wrapper to easily supress synthesizer warnings
from unavailable, unused and unconnected pins.

the project is now organised in a way how the IP core and it's parts are beeing used. this means that the
low-level gpif access module is instantiated by the higher level modules and not the other way around.
this will make more sense when more parts of this IP core are finished (planning is finished, they have
to be implemented and tested now).		 nussgipfel 5449d 00h /gecko3/trunk/GECKO3COM/gecko3com-ip/core/GECKO3COM.ipf

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