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[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [coregenerator/] [coregenerator_fifo_dualclock.xise] - Rev 31

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28 switched to work on the v1 production GECKO3main. the timing is a big issue
with the prototype system. the cabeling and the possibly bad influence of the
prototype board layout makes it impossible to run this core in sync with the
host transfers.

out transfer is fully working. always in sync with the transfers and reads all
tmc headers correctly.

abort handling in the core works as well. there were some fixes needed in the
firmware, not all IN FIFO buffer where flushed.

a lot of work was done for the IN transfer (fpga to pc). the in transfer
handling in GECKO3COM_simple_test.vhd is finished.

the GECKO3COM_simple_datapath/fsm is finished.

there is still an issue left but I think the problem is in the gpif_com
module. for long IN transfers, we still not receive the correct number of bytes.

it works great for all sort of short transfers.


Here I present a time measurement to show the achieved message throughput:
(Response message was 1 byte, total with header and align bytes was 16 byte)

time for i in {0..100000}; do cat /dev/usbtmc1 > /dev/null; done

real 5m45.706s
user 0m27.498s
sys 4m52.676s

This shows that we can read data from the fpga with a rate up to 290 Hz		 nussgipfel 5371d 21h /gecko3/trunk/GECKO3COM/gecko3com-ip/core/coregenerator/coregenerator_fifo_dualclock.xise
24 first version of the GECKO3COM_simple_test that successfully synthesized.
debugging starts now.

fixed a small bug in the gpif_com_test due to the adding of the gpif_com_eom signal and the eom bit
flip-flop in the gpif_com module.		 nussgipfel 5382d 22h /gecko3/trunk/GECKO3COM/gecko3com-ip/core/coregenerator/coregenerator_fifo_dualclock.xise

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