URL https://opencores.org/ocsvn/gecko3/gecko3/trunk

Subversion Repositories gecko3

[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [fifo_dualclock.vhd] - Rev 34

Rev	Log message	Author	Age	Path
18	I achieved now stable OUT transfers (from the PC to the FPGA) with working throtling (when the FPGA consumes data slower than the host delivers). The basics needed for this are implemented in the FPGA like handshaking with the FX2 and clock domain transistion from the Interface clock to the user defined system clock. in the gpif_com_test.vhd is a message rom, containing a prepared answer message to generate an IN transfer. this is needed for the next step.	nussgipfel	5421d 03h	/gecko3/trunk/GECKO3COM/gecko3com-ip/core/fifo_dualclock.vhd
14	reorganising and renaming the stuff in these project. the core will get the name "GECKO3COM_" followed by the type "simple", "plb" or "opb" to follow the naming in the GECKO3 wiki and to show the IP core interface. duplicated fifo corecenerator files are merged together including a wrapper to easily supress synthesizer warnings from unavailable, unused and unconnected pins. the project is now organised in a way how the IP core and it's parts are beeing used. this means that the low-level gpif access module is instantiated by the higher level modules and not the other way around. this will make more sense when more parts of this IP core are finished (planning is finished, they have to be implemented and tested now).	nussgipfel	5449d 00h	/gecko3/trunk/GECKO3COM/gecko3com-ip/core/fifo_dualclock.vhd