URL https://opencores.org/ocsvn/ha1588/ha1588/trunk

Subversion Repositories ha1588

[/] [ha1588/] [tags/] [v1p0/] [rtl/] [reg/] [reg.v] - Rev 28

Rev	Log message	Author	Age	Path
28	Before changing TSU packet parser datapath width from 32b to 8b.	edn_walter	4474d 01h	/ha1588/tags/v1p0/rtl/reg/reg.v
27	Added more bits to the TSU queue information, of which timestamp value is enlarged from 4s to 64s.	edn_walter	4474d 01h	/ha1588/tags/v1p0/rtl/reg/reg.v
24	Added test cases for top-level testbench to cover both RTC and TSU.	edn_walter	4476d 20h	/ha1588/tags/v1p0/rtl/reg/reg.v
23	Added CDC hand-shaking for RTC time reading operation.	edn_walter	4477d 14h	/ha1588/tags/v1p0/rtl/reg/reg.v
21	Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application.	edn_walter	4478d 15h	/ha1588/tags/v1p0/rtl/reg/reg.v
18	Added QuartusII Place and Route project for top level ha1588.v	edn_walter	4482d 19h	/ha1588/tags/v1p0/rtl/reg/reg.v
17	Updated reg.v content.	edn_walter	4483d 13h	/ha1588/tags/v1p0/rtl/reg/reg.v
16	Try to add sth.	edn_walter	4487d 06h	/ha1588/tags/v1p0/rtl/reg/reg.v
15	Renamed module name for tsu and rtc. Added folder for reg and top. Added folder for sopc, preparing for Altera SOPC Builder customized component.	edn_walter	4489d 14h	/ha1588/tags/v1p0/rtl/reg/reg.v