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[/] [ha1588/] [tags/] [v1p2/] [rtl/] [top/] [ha1588.v] - Rev 53

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53 Corrected 2 bugs: SOPC addressing and Wrong Preamble+SFD format. edn_walter 4475d 00h /ha1588/tags/v1p2/rtl/top/ha1588.v
48 1. Added testbench for SOPC Builder example. Need to fully implement the self-check test cases. Just ignore the reported failures, and check the waveform for correct addressing.
2. Added GENERATE BLOCK for top-level addr_in unit selection. In normal top-level instantiation without modify the default addr_is_in_word = 0 parameter, the default address unit is in byte (8bit); When instantiated in SOPC Builder, the address unit is default to word (32bit).		 edn_walter 4480d 00h /ha1588/tags/v1p2/rtl/top/ha1588.v
43 Added software configurable PTP message id mask for TSU parser. edn_walter 4484d 17h /ha1588/tags/v1p2/rtl/top/ha1588.v
41 Added pre-adder to the accumulator to cut down critical timing path. edn_walter 4485d 01h /ha1588/tags/v1p2/rtl/top/ha1588.v
39 1. Added memory map and feature description.
2. Separated TX RX TSU register addresses.		 edn_walter 4485d 05h /ha1588/tags/v1p2/rtl/top/ha1588.v
38 1. Redefined the memory map. See changes in reg.v and ptp_drv_bfm.c.
2. Added adj_done signal for CPU polling.
3. Making time_acc_modulo a constant = 256,000,000,000. No need to change it from software side.		 edn_walter 4486d 02h /ha1588/tags/v1p2/rtl/top/ha1588.v
37 Timestamp format in the queue = null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit edn_walter 4486d 06h /ha1588/tags/v1p2/rtl/top/ha1588.v
34 Added LGPL file header to all copyrighted files. edn_walter 4488d 02h /ha1588/tags/v1p2/rtl/top/ha1588.v
32 Added PTP standard time format output to the top module. Can be connected to external modules. edn_walter 4488d 06h /ha1588/tags/v1p2/rtl/top/ha1588.v
30 Timestamp format in the queue = msgId_4bit + seqId_16bit + null_8bit + timeStamp1s_4bit + null_2bit + timeStamp1ns_30bit edn_walter 4489d 00h /ha1588/tags/v1p2/rtl/top/ha1588.v
27 Added more bits to the TSU queue information, of which timestamp value is enlarged from 4s to 64s. edn_walter 4489d 06h /ha1588/tags/v1p2/rtl/top/ha1588.v
21 Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application. edn_walter 4493d 20h /ha1588/tags/v1p2/rtl/top/ha1588.v
18 Added QuartusII Place and Route project for top level ha1588.v edn_walter 4498d 00h /ha1588/tags/v1p2/rtl/top/ha1588.v

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