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[/] [ha1588/] [trunk/] [rtl/] [reg/] [reg.v] - Rev 30

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27 Added more bits to the TSU queue information, of which timestamp value is enlarged from 4s to 64s. edn_walter 4560d 02h /ha1588/trunk/rtl/reg/reg.v
24 Added test cases for top-level testbench to cover both RTC and TSU. edn_walter 4562d 21h /ha1588/trunk/rtl/reg/reg.v
23 Added CDC hand-shaking for RTC time reading operation. edn_walter 4563d 15h /ha1588/trunk/rtl/reg/reg.v
21 Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application. edn_walter 4564d 16h /ha1588/trunk/rtl/reg/reg.v
18 Added QuartusII Place and Route project for top level ha1588.v edn_walter 4568d 20h /ha1588/trunk/rtl/reg/reg.v
17 Updated reg.v content. edn_walter 4569d 14h /ha1588/trunk/rtl/reg/reg.v
16 Try to add sth. edn_walter 4573d 07h /ha1588/trunk/rtl/reg/reg.v
15 Renamed module name for tsu and rtc.
Added folder for reg and top.
Added folder for sopc, preparing for Altera SOPC Builder customized component.
edn_walter 4575d 15h /ha1588/trunk/rtl/reg/reg.v

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