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[/] [ha1588/] [trunk/] [rtl/] [reg/] [reg.v] - Rev 38

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38 1. Redefined the memory map. See changes in reg.v and ptp_drv_bfm.c.
2. Added adj_done signal for CPU polling.
3. Making time_acc_modulo a constant = 256,000,000,000. No need to change it from software side.		 edn_walter 4612d 13h /ha1588/trunk/rtl/reg/reg.v
37 Timestamp format in the queue = null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit edn_walter 4612d 16h /ha1588/trunk/rtl/reg/reg.v
34 Added LGPL file header to all copyrighted files. edn_walter 4614d 13h /ha1588/trunk/rtl/reg/reg.v
33 Redefined memory map. RTC and TSU now have separate address spans, can be easily divided into to independent modules. edn_walter 4614d 14h /ha1588/trunk/rtl/reg/reg.v
31 Added hand-shaking for the TSU data reading. edn_walter 4615d 10h /ha1588/trunk/rtl/reg/reg.v
27 Added more bits to the TSU queue information, of which timestamp value is enlarged from 4s to 64s. edn_walter 4615d 17h /ha1588/trunk/rtl/reg/reg.v
24 Added test cases for top-level testbench to cover both RTC and TSU. edn_walter 4618d 12h /ha1588/trunk/rtl/reg/reg.v
23 Added CDC hand-shaking for RTC time reading operation. edn_walter 4619d 06h /ha1588/trunk/rtl/reg/reg.v
21 Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application. edn_walter 4620d 07h /ha1588/trunk/rtl/reg/reg.v
18 Added QuartusII Place and Route project for top level ha1588.v edn_walter 4624d 11h /ha1588/trunk/rtl/reg/reg.v
17 Updated reg.v content. edn_walter 4625d 05h /ha1588/trunk/rtl/reg/reg.v
16 Try to add sth. edn_walter 4628d 22h /ha1588/trunk/rtl/reg/reg.v
15 Renamed module name for tsu and rtc.
Added folder for reg and top.
Added folder for sopc, preparing for Altera SOPC Builder customized component.		 edn_walter 4631d 06h /ha1588/trunk/rtl/reg/reg.v

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