OpenCores
URL https://opencores.org/ocsvn/ha1588/ha1588/trunk

Subversion Repositories ha1588

[/] [ha1588/] [trunk/] [rtl/] [reg/] [reg.v] - Rev 77

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
73 Corrected AXI4 wrapper timing bug.
Added system-level instantiation examples for XPS and Qsys.		 ash_riple 3814d 03h /ha1588/trunk/rtl/reg/reg.v
45 1. optimized area, by removing unused registers.
2. optimized timing, by removing latches.		 edn_walter 4593d 15h /ha1588/trunk/rtl/reg/reg.v
43 Added software configurable PTP message id mask for TSU parser. edn_walter 4594d 16h /ha1588/trunk/rtl/reg/reg.v
39 1. Added memory map and feature description.
2. Separated TX RX TSU register addresses.		 edn_walter 4595d 03h /ha1588/trunk/rtl/reg/reg.v
38 1. Redefined the memory map. See changes in reg.v and ptp_drv_bfm.c.
2. Added adj_done signal for CPU polling.
3. Making time_acc_modulo a constant = 256,000,000,000. No need to change it from software side.		 edn_walter 4596d 01h /ha1588/trunk/rtl/reg/reg.v
37 Timestamp format in the queue = null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit edn_walter 4596d 04h /ha1588/trunk/rtl/reg/reg.v
34 Added LGPL file header to all copyrighted files. edn_walter 4598d 01h /ha1588/trunk/rtl/reg/reg.v
33 Redefined memory map. RTC and TSU now have separate address spans, can be easily divided into to independent modules. edn_walter 4598d 02h /ha1588/trunk/rtl/reg/reg.v
31 Added hand-shaking for the TSU data reading. edn_walter 4598d 22h /ha1588/trunk/rtl/reg/reg.v
27 Added more bits to the TSU queue information, of which timestamp value is enlarged from 4s to 64s. edn_walter 4599d 04h /ha1588/trunk/rtl/reg/reg.v
24 Added test cases for top-level testbench to cover both RTC and TSU. edn_walter 4602d 00h /ha1588/trunk/rtl/reg/reg.v
23 Added CDC hand-shaking for RTC time reading operation. edn_walter 4602d 18h /ha1588/trunk/rtl/reg/reg.v
21 Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application. edn_walter 4603d 18h /ha1588/trunk/rtl/reg/reg.v
18 Added QuartusII Place and Route project for top level ha1588.v edn_walter 4607d 23h /ha1588/trunk/rtl/reg/reg.v
17 Updated reg.v content. edn_walter 4608d 16h /ha1588/trunk/rtl/reg/reg.v
16 Try to add sth. edn_walter 4612d 09h /ha1588/trunk/rtl/reg/reg.v
15 Renamed module name for tsu and rtc.
Added folder for reg and top.
Added folder for sopc, preparing for Altera SOPC Builder customized component.		 edn_walter 4614d 18h /ha1588/trunk/rtl/reg/reg.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.