URL https://opencores.org/ocsvn/ha1588/ha1588/trunk

Subversion Repositories ha1588

[/] [ha1588/] [trunk/] [rtl/] [top/] [ha1588.v] - Rev 38

Rev	Log message	Author	Age	Path
38	1. Redefined the memory map. See changes in reg.v and ptp_drv_bfm.c. 2. Added adj_done signal for CPU polling. 3. Making time_acc_modulo a constant = 256,000,000,000. No need to change it from software side.	edn_walter	4612d 15h	/ha1588/trunk/rtl/top/ha1588.v
37	Timestamp format in the queue = null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit	edn_walter	4612d 19h	/ha1588/trunk/rtl/top/ha1588.v
34	Added LGPL file header to all copyrighted files.	edn_walter	4614d 15h	/ha1588/trunk/rtl/top/ha1588.v
32	Added PTP standard time format output to the top module. Can be connected to external modules.	edn_walter	4614d 19h	/ha1588/trunk/rtl/top/ha1588.v
30	Timestamp format in the queue = msgId_4bit + seqId_16bit + null_8bit + timeStamp1s_4bit + null_2bit + timeStamp1ns_30bit	edn_walter	4615d 13h	/ha1588/trunk/rtl/top/ha1588.v
27	Added more bits to the TSU queue information, of which timestamp value is enlarged from 4s to 64s.	edn_walter	4615d 19h	/ha1588/trunk/rtl/top/ha1588.v
21	Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application.	edn_walter	4620d 09h	/ha1588/trunk/rtl/top/ha1588.v
18	Added QuartusII Place and Route project for top level ha1588.v	edn_walter	4624d 13h	/ha1588/trunk/rtl/top/ha1588.v