URL https://opencores.org/ocsvn/ha1588/ha1588/trunk

Subversion Repositories ha1588

[/] [ha1588/] [trunk/] [sim/] [top/] [ha1588_tb.v] - Rev 67

Rev	Log message	Author	Age	Path
58	Added output rtc_time_one_pps for clock accuracy measurement. 1PPS output is leading edge aligned with the PTP time output on boundary of 1s.	edn_walter	4598d 12h	/ha1588/trunk/sim/top/ha1588_tb.v
54	Added support for MII interface as well as GMII interface. Updated unit and top-level test cases.	edn_walter	4599d 10h	/ha1588/trunk/sim/top/ha1588_tb.v
38	1. Redefined the memory map. See changes in reg.v and ptp_drv_bfm.c. 2. Added adj_done signal for CPU polling. 3. Making time_acc_modulo a constant = 256,000,000,000. No need to change it from software side.	edn_walter	4612d 10h	/ha1588/trunk/sim/top/ha1588_tb.v
37	Timestamp format in the queue = null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit	edn_walter	4612d 14h	/ha1588/trunk/sim/top/ha1588_tb.v
34	Added LGPL file header to all copyrighted files.	edn_walter	4614d 11h	/ha1588/trunk/sim/top/ha1588_tb.v
32	Added PTP standard time format output to the top module. Can be connected to external modules.	edn_walter	4614d 14h	/ha1588/trunk/sim/top/ha1588_tb.v
24	Added test cases for top-level testbench to cover both RTC and TSU.	edn_walter	4618d 09h	/ha1588/trunk/sim/top/ha1588_tb.v
21	Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application.	edn_walter	4620d 04h	/ha1588/trunk/sim/top/ha1588_tb.v