OpenCores
URL https://opencores.org/ocsvn/heap_sorter/heap_sorter/trunk

Subversion Repositories heap_sorter

[/] [heap_sorter/] [trunk/] [standard_version/] [src/] [dpram4_synth.vhd] - Rev 5

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
5 Added new high-speed version capable to work at higher speed, but using 4
clk cycles per data word.
wzab 2437d 08h /heap_sorter/trunk/standard_version/src/dpram4_synth.vhd
4 Added file implementing dual port common clock RAM inferrable in synthesis. wzab 4149d 05h /heap_sorter/trunk/src/dpram4_synth.vhd

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.