URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [tags/] [rel_1/] [sim/] [i2c_verilog/] [run/] [bench.vcd] - Rev 69

Rev	Log message	Author	Age	Path
68	New directory structure.	root	5553d 21h	/i2c/tags/rel_1/sim/i2c_verilog/run/bench.vcd
44	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7560d 11h	/i2c/tags/rel_1/sim/i2c_verilog/run/bench.vcd
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	8013d 12h	/i2c/tags/rel_1/sim/i2c_verilog/run/bench.vcd