URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] [bench/] [verilog/] [i2c_slave_model.v] - Rev 68

Rev	Log message	Author	Age	Path
68	New directory structure.	root	5742d 17h	/i2c/trunk/bench/verilog/i2c_slave_model.v
58	fixed (n)ack generation	rherveille	6660d 06h	/i2c/trunk/bench/verilog/i2c_slave_model.v
56	Fixed Tsu:sta timing check. Added Thd:sta timing check.	rherveille	7213d 04h	/i2c/trunk/bench/verilog/i2c_slave_model.v
46	Fixed slave address MSB='1' bug	rherveille	7664d 04h	/i2c/trunk/bench/verilog/i2c_slave_model.v
43	Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'.	rherveille	7749d 07h	/i2c/trunk/bench/verilog/i2c_slave_model.v
25	Added timing tests to i2c_model. Updated testbench.	rherveille	8064d 21h	/i2c/trunk/bench/verilog/i2c_slave_model.v
19	Fixed some race conditions in the i2c-slave model. Added debug information. Added headers.	rherveille	8292d 05h	/i2c/trunk/bench/verilog/i2c_slave_model.v
10	Created new directory structure. Added Verilog version.	rherveille	8466d 03h	/i2c/trunk/bench/verilog/i2c_slave_model.v