URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] [rtl/] [verilog/] [i2c_master_byte_ctrl.v] - Rev 72

Rev	Log message	Author	Age	Path
68	New directory structure.	root	5738d 15h	/i2c/trunk/rtl/verilog/i2c_master_byte_ctrl.v
62	Fixed synopsys miss spell (synopsis) Fixed cr[0] register width Fixed ! usage instead of ~ Fixed bit controller parameter width to 18bits	rherveille	5787d 17h	/i2c/trunk/rtl/verilog/i2c_master_byte_ctrl.v
47	Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.	rherveille	7585d 02h	/i2c/trunk/rtl/verilog/i2c_master_byte_ctrl.v
38	Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. Fixed a potential bug in the byte controller's host-acknowledge generation.	rherveille	7778d 07h	/i2c/trunk/rtl/verilog/i2c_master_byte_ctrl.v
29	Core is now a Multimaster I2C controller	rherveille	8003d 23h	/i2c/trunk/rtl/verilog/i2c_master_byte_ctrl.v
27	Cleaned up code	rherveille	8029d 16h	/i2c/trunk/rtl/verilog/i2c_master_byte_ctrl.v
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8420d 02h	/i2c/trunk/rtl/verilog/i2c_master_byte_ctrl.v
13	Fixed some synthesis warnings.	rherveille	8431d 06h	/i2c/trunk/rtl/verilog/i2c_master_byte_ctrl.v
10	Created new directory structure. Added Verilog version.	rherveille	8462d 02h	/i2c/trunk/rtl/verilog/i2c_master_byte_ctrl.v