OpenCores

URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] [rtl/] [verilog/] [i2c_master_top.v] - Rev 72

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Rev	Log message	Author	Age	Path
68	New directory structure.	root	5738d 16h	/i2c/trunk/rtl/verilog/i2c_master_top.v
62	Fixed synopsys miss spell (synopsis) Fixed cr[0] register width Fixed ! usage instead of ~ Fixed bit controller parameter width to 18bits	rherveille	5787d 18h	/i2c/trunk/rtl/verilog/i2c_master_top.v
55	Fixed register overwrite issue. Removed full_case pragma, replaced it by a default statement.	rherveille	7210d 05h	/i2c/trunk/rtl/verilog/i2c_master_top.v
40	Fix a blocking vs. non-blocking error in the wb_dat output mux.	rherveille	7755d 04h	/i2c/trunk/rtl/verilog/i2c_master_top.v
33	Fixed a bug in the Command Register declaration.	rherveille	7989d 22h	/i2c/trunk/rtl/verilog/i2c_master_top.v
30	Small code simplifications	rherveille	8003d 22h	/i2c/trunk/rtl/verilog/i2c_master_top.v
29	Core is now a Multimaster I2C controller	rherveille	8003d 23h	/i2c/trunk/rtl/verilog/i2c_master_top.v
27	Cleaned up code	rherveille	8029d 16h	/i2c/trunk/rtl/verilog/i2c_master_top.v
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8415d 03h	/i2c/trunk/rtl/verilog/i2c_master_top.v
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8420d 02h	/i2c/trunk/rtl/verilog/i2c_master_top.v
13	Fixed some synthesis warnings.	rherveille	8431d 06h	/i2c/trunk/rtl/verilog/i2c_master_top.v
11	Changed RST_LVL define to parameter.	rherveille	8440d 05h	/i2c/trunk/rtl/verilog/i2c_master_top.v
10	Created new directory structure. Added Verilog version.	rherveille	8462d 02h	/i2c/trunk/rtl/verilog/i2c_master_top.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.