URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] [rtl/] [vhdl/] [i2c_master_top.vhd] - Rev 75

Rev	Log message	Author	Age	Path
71	Fixed double wishbone write in a single access	rherveille	5456d 22h	/i2c/trunk/rtl/vhdl/i2c_master_top.vhd
68	New directory structure.	root	5765d 16h	/i2c/trunk/rtl/vhdl/i2c_master_top.vhd
65	Changed wb_adr_i from unsigned to std_logic_vector	rherveille	5814d 04h	/i2c/trunk/rtl/vhdl/i2c_master_top.vhd
51	Fixed simulation issue when writing to CR register	rherveille	7587d 04h	/i2c/trunk/rtl/vhdl/i2c_master_top.vhd
38	Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. Fixed a potential bug in the byte controller's host-acknowledge generation.	rherveille	7805d 08h	/i2c/trunk/rtl/vhdl/i2c_master_top.vhd
34	Fixed a few 'arbitration lost' bugs. VHDL version only.	rherveille	7994d 12h	/i2c/trunk/rtl/vhdl/i2c_master_top.vhd
31	Core is now a Multimaster I2C controller.	rherveille	8030d 22h	/i2c/trunk/rtl/vhdl/i2c_master_top.vhd
27	Cleaned up code	rherveille	8056d 16h	/i2c/trunk/rtl/vhdl/i2c_master_top.vhd
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8442d 04h	/i2c/trunk/rtl/vhdl/i2c_master_top.vhd
15	Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. Code updated, is now up-to-date to doc. rev.0.4. Added headers.	rherveille	8447d 03h	/i2c/trunk/rtl/vhdl/i2c_master_top.vhd