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[/] [ion/] [trunk/] [src/] [bin2hdl.py] - Rev 90

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Rev Log message Author Age Path
84 Added 'trigger address' for file logging to both the
vhdl TB and the python script
ja_rd 5012d 07h /ion/trunk/src/bin2hdl.py
77 Simulation template now supports simulated flash
Synthesis template adapted to latest cache interface
Python script now supports simulated flash
ja_rd 5022d 04h /ion/trunk/src/bin2hdl.py
56 synthesis mpu template updated:
BRAM is now one 32-bit-wide block instead of 4 8-bitters
(it is read only)
python script updated accordingly
ja_rd 5024d 23h /ion/trunk/src/bin2hdl.py
33 bin2hdl now can initialize 16-bit wide memories ja_rd 5029d 06h /ion/trunk/src/bin2hdl.py
24 changes in simulation test benches:
Simulation length now configurable from the python script
Console output logged to file, not to modelsim's window
ja_rd 5031d 09h /ion/trunk/src/bin2hdl.py
2 First commit (includes 'hello' demo) ja_rd 5034d 09h /ion/trunk/src/bin2hdl.py

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