URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] [src/] [mips_mpu1_template.vhdl] - Rev 142

Rev	Log message	Author	Age	Path
135	Added debug output to synthesizable MPU template.	ja_rd	4926d 08h	/ion/trunk/src/mips_mpu1_template.vhdl
125	MPU templates now use the real cache by default	ja_rd	4929d 06h	/ion/trunk/src/mips_mpu1_template.vhdl
113	Added clock frequency generic to MPU module template (the generics are used by UART submodules)	ja_rd	4984d 14h	/ion/trunk/src/mips_mpu1_template.vhdl
102	ADDED cache control bits to CP0 status register ADDED cache control outputs	ja_rd	4993d 04h	/ion/trunk/src/mips_mpu1_template.vhdl
97	CPU rd and wr data address buses unified	ja_rd	5017d 13h	/ion/trunk/src/mips_mpu1_template.vhdl
87	Added UART RX interface to MPU template	ja_rd	5028d 10h	/ion/trunk/src/mips_mpu1_template.vhdl
77	Simulation template now supports simulated flash Synthesis template adapted to latest cache interface Python script now supports simulated flash	ja_rd	5038d 07h	/ion/trunk/src/mips_mpu1_template.vhdl
65	Fixed io input mux in MPU template 1	ja_rd	5039d 00h	/ion/trunk/src/mips_mpu1_template.vhdl
59	cleaned up top vhdl module of demo moved reset sync ff chain to top module updated pre-generated demo file	ja_rd	5040d 14h	/ion/trunk/src/mips_mpu1_template.vhdl
56	synthesis mpu template updated: BRAM is now one 32-bit-wide block instead of 4 8-bitters (it is read only) python script updated accordingly	ja_rd	5041d 02h	/ion/trunk/src/mips_mpu1_template.vhdl
55	First version of cache: stub, 1-word cache (forgot to commit new mpu template file)	ja_rd	5041d 03h	/ion/trunk/src/mips_mpu1_template.vhdl