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[/] [ion/] [trunk/] [src/] [mips_mpu1_template.vhdl] - Rev 188

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Rev Log message Author Age Path
162 Fixed stupid mistake in headers (date of project) ja_rd 4903d 02h /ion/trunk/src/mips_mpu1_template.vhdl
161 Added GPL license info to the vhdl headers
This project is becoming respectable :)		 ja_rd 4903d 02h /ion/trunk/src/mips_mpu1_template.vhdl
135 Added debug output to synthesizable MPU template. ja_rd 4911d 04h /ion/trunk/src/mips_mpu1_template.vhdl
125 MPU templates now use the real cache by default ja_rd 4914d 02h /ion/trunk/src/mips_mpu1_template.vhdl
113 Added clock frequency generic to MPU module template
(the generics are used by UART submodules)		 ja_rd 4969d 09h /ion/trunk/src/mips_mpu1_template.vhdl
102 ADDED cache control bits to CP0 status register
ADDED cache control outputs		 ja_rd 4978d 00h /ion/trunk/src/mips_mpu1_template.vhdl
97 CPU rd and wr data address buses unified ja_rd 5002d 09h /ion/trunk/src/mips_mpu1_template.vhdl
87 Added UART RX interface to MPU template ja_rd 5013d 05h /ion/trunk/src/mips_mpu1_template.vhdl
77 Simulation template now supports simulated flash
Synthesis template adapted to latest cache interface
Python script now supports simulated flash		 ja_rd 5023d 03h /ion/trunk/src/mips_mpu1_template.vhdl
65 Fixed io input mux in MPU template 1 ja_rd 5023d 19h /ion/trunk/src/mips_mpu1_template.vhdl
59 cleaned up top vhdl module of demo
moved reset sync ff chain to top module
updated pre-generated demo file		 ja_rd 5025d 09h /ion/trunk/src/mips_mpu1_template.vhdl
56 synthesis mpu template updated:
BRAM is now one 32-bit-wide block instead of 4 8-bitters
(it is read only)
python script updated accordingly		 ja_rd 5025d 22h /ion/trunk/src/mips_mpu1_template.vhdl
55 First version of cache: stub, 1-word cache
(forgot to commit new mpu template file)		 ja_rd 5025d 22h /ion/trunk/src/mips_mpu1_template.vhdl

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