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[/] [ion/] [trunk/] [src/] [mips_mpu1_template.vhdl] - Rev 90

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Rev Log message Author Age Path
87 Added UART RX interface to MPU template ja_rd 5028d 00h /ion/trunk/src/mips_mpu1_template.vhdl
77 Simulation template now supports simulated flash
Synthesis template adapted to latest cache interface
Python script now supports simulated flash
ja_rd 5037d 21h /ion/trunk/src/mips_mpu1_template.vhdl
65 Fixed io input mux in MPU template 1 ja_rd 5038d 14h /ion/trunk/src/mips_mpu1_template.vhdl
59 cleaned up top vhdl module of demo
moved reset sync ff chain to top module
updated pre-generated demo file
ja_rd 5040d 03h /ion/trunk/src/mips_mpu1_template.vhdl
56 synthesis mpu template updated:
BRAM is now one 32-bit-wide block instead of 4 8-bitters
(it is read only)
python script updated accordingly
ja_rd 5040d 16h /ion/trunk/src/mips_mpu1_template.vhdl
55 First version of cache: stub, 1-word cache
(forgot to commit new mpu template file)
ja_rd 5040d 16h /ion/trunk/src/mips_mpu1_template.vhdl

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