URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] [src/] [mips_tb2_template.vhdl] - Rev 111

Rev	Log message	Author	Age	Path
104	FIXED typo in last commit for simulation template	ja_rd	4862d 17h	/ion/trunk/src/mips_tb2_template.vhdl
102	ADDED cache control bits to CP0 status register ADDED cache control outputs	ja_rd	4862d 18h	/ion/trunk/src/mips_tb2_template.vhdl
97	CPU rd and wr data address buses unified	ja_rd	4887d 03h	/ion/trunk/src/mips_tb2_template.vhdl
86	Adapted TB template to use log trigger address	ja_rd	4898d 00h	/ion/trunk/src/mips_tb2_template.vhdl
77	Simulation template now supports simulated flash Synthesis template adapted to latest cache interface Python script now supports simulated flash	ja_rd	4907d 21h	/ion/trunk/src/mips_tb2_template.vhdl
74	Fixed (harmless) error in simulation template 2	ja_rd	4908d 01h	/ion/trunk/src/mips_tb2_template.vhdl
51	Adapted simulation and synth templates for cache module	ja_rd	4910d 19h	/ion/trunk/src/mips_tb2_template.vhdl
42	Added cache stub module, plus related test bench	ja_rd	4914d 22h	/ion/trunk/src/mips_tb2_template.vhdl