URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] [src/] [mips_tb2_template.vhdl] - Rev 160

Rev	Log message	Author	Age	Path
137	Updated TB2 for new cache interface ('unmapped' signal)	ja_rd	4911d 10h	/ion/trunk/src/mips_tb2_template.vhdl
125	MPU templates now use the real cache by default	ja_rd	4914d 08h	/ion/trunk/src/mips_tb2_template.vhdl
104	FIXED typo in last commit for simulation template	ja_rd	4978d 05h	/ion/trunk/src/mips_tb2_template.vhdl
102	ADDED cache control bits to CP0 status register ADDED cache control outputs	ja_rd	4978d 06h	/ion/trunk/src/mips_tb2_template.vhdl
97	CPU rd and wr data address buses unified	ja_rd	5002d 15h	/ion/trunk/src/mips_tb2_template.vhdl
86	Adapted TB template to use log trigger address	ja_rd	5013d 12h	/ion/trunk/src/mips_tb2_template.vhdl
77	Simulation template now supports simulated flash Synthesis template adapted to latest cache interface Python script now supports simulated flash	ja_rd	5023d 09h	/ion/trunk/src/mips_tb2_template.vhdl
74	Fixed (harmless) error in simulation template 2	ja_rd	5023d 13h	/ion/trunk/src/mips_tb2_template.vhdl
51	Adapted simulation and synth templates for cache module	ja_rd	5026d 07h	/ion/trunk/src/mips_tb2_template.vhdl
42	Added cache stub module, plus related test bench	ja_rd	5030d 10h	/ion/trunk/src/mips_tb2_template.vhdl