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[/] [ion/] [trunk/] [src/] [mips_tb2_template.vhdl] - Rev 220

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Rev Log message Author Age Path
196 Marked old TB template as obsolete.
I'm not comfortable removing it yet. Silly, that.		 ja_rd 4871d 13h /ion/trunk/src/mips_tb2_template.vhdl
162 Fixed stupid mistake in headers (date of project) ja_rd 4921d 19h /ion/trunk/src/mips_tb2_template.vhdl
161 Added GPL license info to the vhdl headers
This project is becoming respectable :)		 ja_rd 4921d 19h /ion/trunk/src/mips_tb2_template.vhdl
137 Updated TB2 for new cache interface ('unmapped' signal) ja_rd 4929d 21h /ion/trunk/src/mips_tb2_template.vhdl
125 MPU templates now use the real cache by default ja_rd 4932d 19h /ion/trunk/src/mips_tb2_template.vhdl
104 FIXED typo in last commit for simulation template ja_rd 4996d 17h /ion/trunk/src/mips_tb2_template.vhdl
102 ADDED cache control bits to CP0 status register
ADDED cache control outputs		 ja_rd 4996d 17h /ion/trunk/src/mips_tb2_template.vhdl
97 CPU rd and wr data address buses unified ja_rd 5021d 02h /ion/trunk/src/mips_tb2_template.vhdl
86 Adapted TB template to use log trigger address ja_rd 5031d 23h /ion/trunk/src/mips_tb2_template.vhdl
77 Simulation template now supports simulated flash
Synthesis template adapted to latest cache interface
Python script now supports simulated flash		 ja_rd 5041d 20h /ion/trunk/src/mips_tb2_template.vhdl
74 Fixed (harmless) error in simulation template 2 ja_rd 5042d 00h /ion/trunk/src/mips_tb2_template.vhdl
51 Adapted simulation and synth templates for cache module ja_rd 5044d 19h /ion/trunk/src/mips_tb2_template.vhdl
42 Added cache stub module, plus related test bench ja_rd 5048d 21h /ion/trunk/src/mips_tb2_template.vhdl

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