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[/] [ion/] [trunk/] [src/] [mips_tb2_template.vhdl] - Rev 231

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Rev Log message Author Age Path
196 Marked old TB template as obsolete.
I'm not comfortable removing it yet. Silly, that.		 ja_rd 4876d 01h /ion/trunk/src/mips_tb2_template.vhdl
162 Fixed stupid mistake in headers (date of project) ja_rd 4926d 08h /ion/trunk/src/mips_tb2_template.vhdl
161 Added GPL license info to the vhdl headers
This project is becoming respectable :)		 ja_rd 4926d 08h /ion/trunk/src/mips_tb2_template.vhdl
137 Updated TB2 for new cache interface ('unmapped' signal) ja_rd 4934d 10h /ion/trunk/src/mips_tb2_template.vhdl
125 MPU templates now use the real cache by default ja_rd 4937d 08h /ion/trunk/src/mips_tb2_template.vhdl
104 FIXED typo in last commit for simulation template ja_rd 5001d 05h /ion/trunk/src/mips_tb2_template.vhdl
102 ADDED cache control bits to CP0 status register
ADDED cache control outputs		 ja_rd 5001d 05h /ion/trunk/src/mips_tb2_template.vhdl
97 CPU rd and wr data address buses unified ja_rd 5025d 15h /ion/trunk/src/mips_tb2_template.vhdl
86 Adapted TB template to use log trigger address ja_rd 5036d 11h /ion/trunk/src/mips_tb2_template.vhdl
77 Simulation template now supports simulated flash
Synthesis template adapted to latest cache interface
Python script now supports simulated flash		 ja_rd 5046d 08h /ion/trunk/src/mips_tb2_template.vhdl
74 Fixed (harmless) error in simulation template 2 ja_rd 5046d 13h /ion/trunk/src/mips_tb2_template.vhdl
51 Adapted simulation and synth templates for cache module ja_rd 5049d 07h /ion/trunk/src/mips_tb2_template.vhdl
42 Added cache stub module, plus related test bench ja_rd 5053d 10h /ion/trunk/src/mips_tb2_template.vhdl

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