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[/] [ion/] [trunk/] [src/] [mips_tb2_template.vhdl] - Rev 99

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Rev Log message Author Age Path
97 CPU rd and wr data address buses unified ja_rd 5024d 20h /ion/trunk/src/mips_tb2_template.vhdl
86 Adapted TB template to use log trigger address ja_rd 5035d 17h /ion/trunk/src/mips_tb2_template.vhdl
77 Simulation template now supports simulated flash
Synthesis template adapted to latest cache interface
Python script now supports simulated flash
ja_rd 5045d 14h /ion/trunk/src/mips_tb2_template.vhdl
74 Fixed (harmless) error in simulation template 2 ja_rd 5045d 19h /ion/trunk/src/mips_tb2_template.vhdl
51 Adapted simulation and synth templates for cache module ja_rd 5048d 13h /ion/trunk/src/mips_tb2_template.vhdl
42 Added cache stub module, plus related test bench ja_rd 5052d 15h /ion/trunk/src/mips_tb2_template.vhdl

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