OpenCores
URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] [src/] [opcodes/] [opcodes.s] - Rev 115

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
110 Updated 'opcodes' code sample:
- Longer simulated time for compatibility to new cache
ja_rd 4978d 05h /ion/trunk/src/opcodes/opcodes.s
90 Added 'Adventure' demo to be run from the DE-1 FLASH ja_rd 5022d 02h /ion/trunk/src/opcodes/opcodes.s
66 Code samples:
Updated all code samples to use TB2 template and new memory map
ja_rd 5032d 16h /ion/trunk/src/opcodes/opcodes.s
38 Minor changes in header comments ja_rd 5039d 01h /ion/trunk/src/opcodes/opcodes.s
29 opcode test updated:
supports CP0 cause register and traps in delay slots
tests that traps abort next instruction in all cases
ja_rd 5040d 23h /ion/trunk/src/opcodes/opcodes.s
25 opcode test:
HO and LO registers tested along with mul/div and not separately
ja_rd 5041d 04h /ion/trunk/src/opcodes/opcodes.s
14 Opcode test now has mul/div tests enabled by default ja_rd 5042d 15h /ion/trunk/src/opcodes/opcodes.s
9 Trap handling now works as in the MIPS specs:
EPC points to victim instruction (break/syscall)
Opcode test modified accordingly
ja_rd 5043d 16h /ion/trunk/src/opcodes/opcodes.s
4 New test for BREAK: abortion of load and jump
Added comment to readme file
ja_rd 5043d 19h /ion/trunk/src/opcodes/opcodes.s
2 First commit (includes 'hello' demo) ja_rd 5044d 05h /ion/trunk/src/opcodes/opcodes.s

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.