OpenCores
URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] [tools/] [slite/] [src/] [slite.c] - Rev 228

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
228 SW simulator updated
Simulation of UART adapted to new hardware.
Added simulation of debug registers.
ja_rd 4541d 01h /ion/trunk/tools/slite/src/slite.c
208 Bug fix in SW simulator
Crashed when a function call trace log was requested with missing map file
ja_rd 4817d 17h /ion/trunk/tools/slite/src/slite.c
201 Minor fixes to code comments ja_rd 4865d 19h /ion/trunk/tools/slite/src/slite.c
187 Fixed SW simulator: reset value for timer prescaler ja_rd 4904d 02h /ion/trunk/tools/slite/src/slite.c
186 Updated the SW simulator:
Fixed handling of KU/IE flags
Added preliminary support for simulated HW interrupts
Added preliminary support for timer/counter
Enlarged the BRAM in all memory maps (to be undone)
ja_rd 4904d 02h /ion/trunk/tools/slite/src/slite.c
170 Fixed bug in optional emulation of EXT, INS ja_rd 4911d 15h /ion/trunk/tools/slite/src/slite.c
169 Fixed bug in emulation of CLO instruction
Added support for simulated hardware IRQs (incomplete)
ja_rd 4911d 15h /ion/trunk/tools/slite/src/slite.c
166 Modified simulator, added some debug functionality:
- Optional emulation of some MIPS32r2 opcodes
- Function call trace log using map file (crude implementation)

Plus a few small bug fixes
ja_rd 4911d 16h /ion/trunk/tools/slite/src/slite.c
163 SW simulator update:
Better disassembly format (hastily tested)
New parameters: start address, breakpoint address, whether or not to trap reserved opcodes
ja_rd 4917d 02h /ion/trunk/tools/slite/src/slite.c
152 Added R3000 compatible support for kernel/user state:
- Implemented KU/IE plus KUp/IEp and KUo/IEo status bits
- Updated startup and test code to account for changes
- Implemented bit DID NOT TEST rfe instruction (not used in code)
- Access to CP0 in user mode triggers 'CpU' trap
- Updated software simulator

Besides, the logging of HI/LO register changes has been temporarily disabled, there's an unfixed bug in it.
ja_rd 4920d 21h /ion/trunk/tools/slite/src/slite.c
147 SW simulator updated to latest HW revision
(plus a few mistakes corrected: wrongly commented out lines, mostly)
ja_rd 4923d 10h /ion/trunk/tools/slite/src/slite.c
108 Added new 'small' memory map to SW simulator
(so that memtest simulations can be shorter)
ja_rd 4984d 01h /ion/trunk/tools/slite/src/slite.c
105 SW simulator updated:
- New command line options
- New optional memory map
- Runs on batch mode
- Other features for running uClinux
ja_rd 4988d 00h /ion/trunk/tools/slite/src/slite.c
93 SW simulator supports 'log trigger address' and keyboard input as simulated UART RX.
Project parameters now launch adventure demo automatically
ja_rd 5027d 20h /ion/trunk/tools/slite/src/slite.c
61 SW simulator updated:
new mips-1 memory map and trap addresses
slightly better command line argument parsing
ja_rd 5038d 11h /ion/trunk/tools/slite/src/slite.c
53 SW simulator: Major change in logging code.
Changes are logged now with the address of the instruction that caused them.
These changes make the HW simulation TB's life easier.
ja_rd 5040d 16h /ion/trunk/tools/slite/src/slite.c
44 slite: cleaned up memory allocation/deallocation code ja_rd 5042d 20h /ion/trunk/tools/slite/src/slite.c
32 slite: catch 1-instruction endless loops
now can run unattended; will stop at the end of main()
ja_rd 5044d 21h /ion/trunk/tools/slite/src/slite.c
31 Major refactor in slite:
supports memory map with more than 1 block
indentation made homogeneous
unused code removed
ja_rd 5044d 21h /ion/trunk/tools/slite/src/slite.c
27 SW simulator updated: now supports CP0 cause register and traps in delay slots ja_rd 5046d 19h /ion/trunk/tools/slite/src/slite.c

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.