OpenCores
URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] [tools/] [slite/] [src/] [slite.c] - Rev 152

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
152 Added R3000 compatible support for kernel/user state:
- Implemented KU/IE plus KUp/IEp and KUo/IEo status bits
- Updated startup and test code to account for changes
- Implemented bit DID NOT TEST rfe instruction (not used in code)
- Access to CP0 in user mode triggers 'CpU' trap
- Updated software simulator

Besides, the logging of HI/LO register changes has been temporarily disabled, there's an unfixed bug in it.		 ja_rd 4921d 10h /ion/trunk/tools/slite/src/slite.c
147 SW simulator updated to latest HW revision
(plus a few mistakes corrected: wrongly commented out lines, mostly)		 ja_rd 4924d 00h /ion/trunk/tools/slite/src/slite.c
108 Added new 'small' memory map to SW simulator
(so that memtest simulations can be shorter)		 ja_rd 4984d 14h /ion/trunk/tools/slite/src/slite.c
105 SW simulator updated:
- New command line options
- New optional memory map
- Runs on batch mode
- Other features for running uClinux		 ja_rd 4988d 13h /ion/trunk/tools/slite/src/slite.c
93 SW simulator supports 'log trigger address' and keyboard input as simulated UART RX.
Project parameters now launch adventure demo automatically		 ja_rd 5028d 10h /ion/trunk/tools/slite/src/slite.c
61 SW simulator updated:
new mips-1 memory map and trap addresses
slightly better command line argument parsing		 ja_rd 5039d 00h /ion/trunk/tools/slite/src/slite.c
53 SW simulator: Major change in logging code.
Changes are logged now with the address of the instruction that caused them.
These changes make the HW simulation TB's life easier.		 ja_rd 5041d 06h /ion/trunk/tools/slite/src/slite.c
44 slite: cleaned up memory allocation/deallocation code ja_rd 5043d 10h /ion/trunk/tools/slite/src/slite.c
32 slite: catch 1-instruction endless loops
now can run unattended; will stop at the end of main()		 ja_rd 5045d 10h /ion/trunk/tools/slite/src/slite.c
31 Major refactor in slite:
supports memory map with more than 1 block
indentation made homogeneous
unused code removed		 ja_rd 5045d 10h /ion/trunk/tools/slite/src/slite.c
27 SW simulator updated: now supports CP0 cause register and traps in delay slots ja_rd 5047d 09h /ion/trunk/tools/slite/src/slite.c
16 SW simulator now shows HI and LO in status ja_rd 5048d 23h /ion/trunk/tools/slite/src/slite.c
11 SW signed multiplication simulation now lets compiler do the 64-bit arithmetic ja_rd 5049d 10h /ion/trunk/tools/slite/src/slite.c
7 Traps are now simulated as per MIPS specifications:
EPC point to victim instruction (break/syscall)		 ja_rd 5050d 00h /ion/trunk/tools/slite/src/slite.c
5 SW simulator now logs failed assertions instead of quitting ja_rd 5050d 03h /ion/trunk/tools/slite/src/slite.c
2 First commit (includes 'hello' demo) ja_rd 5050d 13h /ion/trunk/tools/slite/src/slite.c

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.