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[/] [ion/] [trunk/] [tools/] [slite/] [src/] [slite.c] - Rev 95

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93 SW simulator supports 'log trigger address' and keyboard input as simulated UART RX.
Project parameters now launch adventure demo automatically		 ja_rd 4970d 05h /ion/trunk/tools/slite/src/slite.c
61 SW simulator updated:
new mips-1 memory map and trap addresses
slightly better command line argument parsing		 ja_rd 4980d 20h /ion/trunk/tools/slite/src/slite.c
53 SW simulator: Major change in logging code.
Changes are logged now with the address of the instruction that caused them.
These changes make the HW simulation TB's life easier.		 ja_rd 4983d 01h /ion/trunk/tools/slite/src/slite.c
44 slite: cleaned up memory allocation/deallocation code ja_rd 4985d 05h /ion/trunk/tools/slite/src/slite.c
32 slite: catch 1-instruction endless loops
now can run unattended; will stop at the end of main()		 ja_rd 4987d 06h /ion/trunk/tools/slite/src/slite.c
31 Major refactor in slite:
supports memory map with more than 1 block
indentation made homogeneous
unused code removed		 ja_rd 4987d 06h /ion/trunk/tools/slite/src/slite.c
27 SW simulator updated: now supports CP0 cause register and traps in delay slots ja_rd 4989d 04h /ion/trunk/tools/slite/src/slite.c
16 SW simulator now shows HI and LO in status ja_rd 4990d 18h /ion/trunk/tools/slite/src/slite.c
11 SW signed multiplication simulation now lets compiler do the 64-bit arithmetic ja_rd 4991d 06h /ion/trunk/tools/slite/src/slite.c
7 Traps are now simulated as per MIPS specifications:
EPC point to victim instruction (break/syscall)		 ja_rd 4991d 20h /ion/trunk/tools/slite/src/slite.c
5 SW simulator now logs failed assertions instead of quitting ja_rd 4991d 22h /ion/trunk/tools/slite/src/slite.c
2 First commit (includes 'hello' demo) ja_rd 4992d 08h /ion/trunk/tools/slite/src/slite.c

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