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[/] [ion/] [trunk/] [vhdl/] [demo/] [c2sb_demo.vhdl] - Rev 209

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Rev	Log message	Author	Age	Path
200	CPU interrupt input changed to 8-bit vector Other modules changed accordingly Interrupts still missing; this is just preparing the interface	ja_rd	4866d 09h	/ion/trunk/vhdl/demo/c2sb_demo.vhdl
162	Fixed stupid mistake in headers (date of project)	ja_rd	4918d 07h	/ion/trunk/vhdl/demo/c2sb_demo.vhdl
161	Added GPL license info to the vhdl headers This project is becoming respectable :)	ja_rd	4918d 07h	/ion/trunk/vhdl/demo/c2sb_demo.vhdl
136	Added debug output to synthesizable MPU template, and connected debug signals to LEDs	ja_rd	4926d 09h	/ion/trunk/vhdl/demo/c2sb_demo.vhdl
116	Updated demo 'top' file for DE-1 board - Added reset button debouncing - Added template for using different clock input - Uses clock rate generic	ja_rd	4984d 11h	/ion/trunk/vhdl/demo/c2sb_demo.vhdl
75	Added support for 8-bit-wide static memory (e.g. Flash) Updated demo 'top' file to use the DE-1 onboard flash	ja_rd	5038d 08h	/ion/trunk/vhdl/demo/c2sb_demo.vhdl
63	DE-1 demo top module: added registers for SD interface, switches and 7-seg display	ja_rd	5039d 01h	/ion/trunk/vhdl/demo/c2sb_demo.vhdl
59	cleaned up top vhdl module of demo moved reset sync ff chain to top module updated pre-generated demo file	ja_rd	5040d 15h	/ion/trunk/vhdl/demo/c2sb_demo.vhdl
46	First version of cache: stub, 1-word cache Stub cache tested on simulation and HW, just a stub Adapted CPU stall logic to 1st version of cache Adapted all other modules for compatibility with cache	ja_rd	5041d 07h	/ion/trunk/vhdl/demo/c2sb_demo.vhdl
2	First commit (includes 'hello' demo)	ja_rd	5050d 14h	/ion/trunk/vhdl/demo/c2sb_demo.vhdl

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