URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] [vhdl/] [mips_cache.vhdl] - Rev 228

Rev	Log message	Author	Age	Path
212	BUG FIX: sequences of back-to-back I/O reads or writes didn't work. The stall conditions were wrong for those cases. Minor cleanup of the comments	ja_rd	4539d 13h	/ion/trunk/vhdl/mips_cache.vhdl
201	Minor fixes to code comments	ja_rd	4853d 08h	/ion/trunk/vhdl/mips_cache.vhdl
162	Fixed stupid mistake in headers (date of project)	ja_rd	4905d 06h	/ion/trunk/vhdl/mips_cache.vhdl
161	Added GPL license info to the vhdl headers This project is becoming respectable :)	ja_rd	4905d 06h	/ion/trunk/vhdl/mips_cache.vhdl
151	BUG FIX: major bugs fixed in cache module 1.- sram address was wrong (leftover from previous version) 2.- writes to unmapped areas were blocking the cache 3.- Sequence SW,LW produced a RAW data hazard in some cases	ja_rd	4908d 11h	/ion/trunk/vhdl/mips_cache.vhdl
145	MAJOR UPDATE: first version of D-Cache	ja_rd	4911d 01h	/ion/trunk/vhdl/mips_cache.vhdl
141	BUG FIX in cache: cpu stall logic was missing key case 2nd SW in a (cached) row was not being stalled	ja_rd	4912d 15h	/ion/trunk/vhdl/mips_cache.vhdl
134	Added 'unmapped access' flag to CPU core, meant for debug mostly. Eventually this flag will trigger an interrupt.	ja_rd	4913d 08h	/ion/trunk/vhdl/mips_cache.vhdl
114	ADDED: 1st version of real cache	ja_rd	4971d 12h	/ion/trunk/vhdl/mips_cache.vhdl