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[/] [ion/] [trunk/] [vhdl/] [mips_cache_stub.vhdl] - Rev 72

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Rev Log message Author Age Path
72 Fixed stupid bug in SRAM write cycles (setup time violated)
Wait states implemented for SRAM wait and read cycles
ja_rd 5147d 03h /ion/trunk/vhdl/mips_cache_stub.vhdl
64 Refactored memory decoding logic
(wait states and read-only attributes unimplemented yet)
ja_rd 5147d 15h /ion/trunk/vhdl/mips_cache_stub.vhdl
58 Cleaned up cache stub code ja_rd 5149d 16h /ion/trunk/vhdl/mips_cache_stub.vhdl
46 First version of cache: stub, 1-word cache
Stub cache tested on simulation and HW, just a stub
Adapted CPU stall logic to 1st version of cache
Adapted all other modules for compatibility with cache
ja_rd 5149d 21h /ion/trunk/vhdl/mips_cache_stub.vhdl
43 added comments to dummy 'cache' stub ja_rd 5152d 05h /ion/trunk/vhdl/mips_cache_stub.vhdl
42 Added cache stub module, plus related test bench ja_rd 5154d 00h /ion/trunk/vhdl/mips_cache_stub.vhdl

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