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[/] [ion/] [trunk/] [vhdl/] [mips_cpu.vhdl] - Rev 104

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Rev	Log message	Author	Age	Path
101	FIX: code_rd_vma asserted only after reset is done ADDED cache control bits to CP0 status register ADDED cache control outputs	ja_rd	4996d 11h	/ion/trunk/vhdl/mips_cpu.vhdl
96	CPU rd and wr data address buses unified	ja_rd	5020d 20h	/ion/trunk/vhdl/mips_cpu.vhdl
83	BUG FIX: LHU was not doing sign extension properly BUG FIX: SLTIU decoding was wrong	ja_rd	5031d 17h	/ion/trunk/vhdl/mips_cpu.vhdl
62	CPU fixed: fixed bug in EPC load logic relative to mem_wait stalls parametrized reset and trap vector addresses	ja_rd	5042d 07h	/ion/trunk/vhdl/mips_cpu.vhdl
46	First version of cache: stub, 1-word cache Stub cache tested on simulation and HW, just a stub Adapted CPU stall logic to 1st version of cache Adapted all other modules for compatibility with cache	ja_rd	5044d 13h	/ion/trunk/vhdl/mips_cpu.vhdl
35	CPU mem_wait logic updated to work with cache	ja_rd	5048d 16h	/ion/trunk/vhdl/mips_cpu.vhdl
30	Completed decoding of instructions (to prevent side effects of invalid opcodes)	ja_rd	5050d 13h	/ion/trunk/vhdl/mips_cpu.vhdl
28	Core updated: supports CP0 cause register and traps in delay slots traps abort next instruction in all cases (incl. jumps/L/S)	ja_rd	5050d 15h	/ion/trunk/vhdl/mips_cpu.vhdl
23	Unimplemented instruction are now trapped (barely tested)	ja_rd	5050d 20h	/ion/trunk/vhdl/mips_cpu.vhdl
22	FIXED killer bug in instruction decoder for beq & mfc0 Decoding was incomplete and beq was using wrong ALU input	ja_rd	5051d 17h	/ion/trunk/vhdl/mips_cpu.vhdl
12	Adapted multiplier unit from Plasma	ja_rd	5052d 06h	/ion/trunk/vhdl/mips_cpu.vhdl
8	Trap handling now works as in the MIPS specs: EPC points to victim instruction (break/syscall)	ja_rd	5053d 07h	/ion/trunk/vhdl/mips_cpu.vhdl
6	Fix: BREAK now aborts load and jump instructions properly	ja_rd	5053d 10h	/ion/trunk/vhdl/mips_cpu.vhdl
2	First commit (includes 'hello' demo)	ja_rd	5053d 20h	/ion/trunk/vhdl/mips_cpu.vhdl

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