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[/] [ion/] [trunk/] [vhdl/] [mips_cpu.vhdl] - Rev 215

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Rev	Log message	Author	Age	Path
200	CPU interrupt input changed to 8-bit vector Other modules changed accordingly Interrupts still missing; this is just preparing the interface	ja_rd	4851d 01h	/ion/trunk/vhdl/mips_cpu.vhdl
171	CPU bug fix: MFC0 instructions aborted by privilege trap should not modify any register	ja_rd	4896d 11h	/ion/trunk/vhdl/mips_cpu.vhdl
162	Fixed stupid mistake in headers (date of project)	ja_rd	4902d 23h	/ion/trunk/vhdl/mips_cpu.vhdl
161	Added GPL license info to the vhdl headers This project is becoming respectable :)	ja_rd	4902d 23h	/ion/trunk/vhdl/mips_cpu.vhdl
159	bug detected but not fixed in cpu (1st instruction after entering user mode is executed in kernel mode)	ja_rd	4904d 08h	/ion/trunk/vhdl/mips_cpu.vhdl
157	Bug fix in the missing coprocesor exception. The CPU was triggering a privilege exception for the mtc0 that went into user mode. Logging HDL updated	ja_rd	4905d 18h	/ion/trunk/vhdl/mips_cpu.vhdl
153	Added R3000 compatible support for kernel/user state: - Implemented KU/IE plus KUp/IEp and KUo/IEo status bits - Updated startup and test code to account for changes - Implemented bit DID NOT TEST rfe instruction (not used in code) - Access to CP0 in user mode triggers 'CpU' trap - Updated software simulator Besides, the logging of HI/LO register changes has been temporarily disabled, there's an unfixed bug in it.	ja_rd	4906d 03h	/ion/trunk/vhdl/mips_cpu.vhdl
140	BUG FIX in cpu: MTCx was using Rs as source instead of Rt BUG FIX in cpu: cached sequences of S* were failing, byte_we logic was wrong	ja_rd	4910d 07h	/ion/trunk/vhdl/mips_cpu.vhdl
132	Fixed bug in stall logic (stall for back-to-back SW instructions was wrong)	ja_rd	4913d 23h	/ion/trunk/vhdl/mips_cpu.vhdl
121	CPU code reorganized a bit No new logic, just a few swapped lines and new comments	ja_rd	4959d 23h	/ion/trunk/vhdl/mips_cpu.vhdl
101	FIX: code_rd_vma asserted only after reset is done ADDED cache control bits to CP0 status register ADDED cache control outputs	ja_rd	4977d 21h	/ion/trunk/vhdl/mips_cpu.vhdl
96	CPU rd and wr data address buses unified	ja_rd	5002d 06h	/ion/trunk/vhdl/mips_cpu.vhdl
83	BUG FIX: LHU was not doing sign extension properly BUG FIX: SLTIU decoding was wrong	ja_rd	5013d 03h	/ion/trunk/vhdl/mips_cpu.vhdl
62	CPU fixed: fixed bug in EPC load logic relative to mem_wait stalls parametrized reset and trap vector addresses	ja_rd	5023d 17h	/ion/trunk/vhdl/mips_cpu.vhdl
46	First version of cache: stub, 1-word cache Stub cache tested on simulation and HW, just a stub Adapted CPU stall logic to 1st version of cache Adapted all other modules for compatibility with cache	ja_rd	5025d 22h	/ion/trunk/vhdl/mips_cpu.vhdl
35	CPU mem_wait logic updated to work with cache	ja_rd	5030d 02h	/ion/trunk/vhdl/mips_cpu.vhdl
30	Completed decoding of instructions (to prevent side effects of invalid opcodes)	ja_rd	5031d 23h	/ion/trunk/vhdl/mips_cpu.vhdl
28	Core updated: supports CP0 cause register and traps in delay slots traps abort next instruction in all cases (incl. jumps/L/S)	ja_rd	5032d 00h	/ion/trunk/vhdl/mips_cpu.vhdl
23	Unimplemented instruction are now trapped (barely tested)	ja_rd	5032d 05h	/ion/trunk/vhdl/mips_cpu.vhdl
22	FIXED killer bug in instruction decoder for beq & mfc0 Decoding was incomplete and beq was using wrong ALU input	ja_rd	5033d 02h	/ion/trunk/vhdl/mips_cpu.vhdl

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[/] [ion/] [trunk/] [vhdl/] [mips_cpu.vhdl] - Rev 215

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