URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] [vhdl/] [tb/] [mips_tb.vhdl] - Rev 224

Rev	Log message	Author	Age	Path
211	Included a simulated block of I/O regs in the test bench for easing some cache tests.	ja_rd	4537d 09h	/ion/trunk/vhdl/tb/mips_tb.vhdl
207	Simulation memories now modelled with shared variables and not signals. This improves simulation speed of large programs (e.g. Adventure) by orders of magnitude	ja_rd	4816d 04h	/ion/trunk/vhdl/tb/mips_tb.vhdl
205	Fixed bug in test bench interface to CPU	ja_rd	4837d 03h	/ion/trunk/vhdl/tb/mips_tb.vhdl
200	CPU interrupt input changed to 8-bit vector Other modules changed accordingly Interrupts still missing; this is just preparing the interface	ja_rd	4851d 03h	/ion/trunk/vhdl/tb/mips_tb.vhdl
193	Major test bench reorganization: 1.- TB now uses same object code as synthesizable demo. 2.- TB now simulates full MPU system. 3.- Console logging moved to TB package. 4.- Code sample makefiles and modelsim script updated accordingly.	ja_rd	4852d 19h	/ion/trunk/vhdl/tb/mips_tb.vhdl