URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] [vhdl/] [tb/] [mips_tb_pkg.vhdl] - Rev 201

Rev	Log message	Author	Age	Path
193	Major test bench reorganization: 1.- TB now uses same object code as synthesizable demo. 2.- TB now simulates full MPU system. 3.- Console logging moved to TB package. 4.- Code sample makefiles and modelsim script updated accordingly.	ja_rd	4852d 20h	/ion/trunk/vhdl/tb/mips_tb_pkg.vhdl
157	Bug fix in the missing coprocesor exception. The CPU was triggering a privilege exception for the mtc0 that went into user mode. Logging HDL updated	ja_rd	4905d 21h	/ion/trunk/vhdl/tb/mips_tb_pkg.vhdl
152	Added R3000 compatible support for kernel/user state: - Implemented KU/IE plus KUp/IEp and KUo/IEo status bits - Updated startup and test code to account for changes - Implemented bit DID NOT TEST rfe instruction (not used in code) - Access to CP0 in user mode triggers 'CpU' trap - Updated software simulator Besides, the logging of HI/LO register changes has been temporarily disabled, there's an unfixed bug in it.	ja_rd	4906d 06h	/ion/trunk/vhdl/tb/mips_tb_pkg.vhdl
112	Updated simulation package for compatibility to new cache	ja_rd	4969d 09h	/ion/trunk/vhdl/tb/mips_tb_pkg.vhdl
96	CPU rd and wr data address buses unified	ja_rd	5002d 09h	/ion/trunk/vhdl/tb/mips_tb_pkg.vhdl
84	Added 'trigger address' for file logging to both the vhdl TB and the python script	ja_rd	5013d 06h	/ion/trunk/vhdl/tb/mips_tb_pkg.vhdl
60	Forgot to upload new TB package!! Without this, simulations don't work...	ja_rd	5023d 20h	/ion/trunk/vhdl/tb/mips_tb_pkg.vhdl