URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

[/] [iso7816_3_master/] [trunk/] [test/] [FiDiAnalyzer.v] - Rev 18

Rev	Log message	Author	Age	Path
18	A bunch of synthesis error/warning removed. Master and analyzer synthesis OK on Spartan6 FPGA	acapola	4996d 10h	/iso7816_3_master/trunk/test/FiDiAnalyzer.v
12	pps sequence added to test bench endOfTx added to TxCore	acapola	5033d 07h	/iso7816_3_master/trunk/test/FiDiAnalyzer.v
11	added BSD licence header to files	acapola	5033d 11h	/iso7816_3_master/trunk/test/FiDiAnalyzer.v
10	communication direction probe added	acapola	5033d 12h	/iso7816_3_master/trunk/test/FiDiAnalyzer.v
6	analyzer added to test bench, not functional yet...	acapola	5043d 07h	/iso7816_3_master/trunk/test/FiDiAnalyzer.v
5	draft of t=0 protocol analyzer (to ease debuging, and eventually as an ip itself)	acapola	5044d 07h	/iso7816_3_master/trunk/test/FiDiAnalyzer.v