URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

[/] [iso7816_3_master/] [trunk/] [test/] [tbIso7816_3_Master.v] - Rev 12

Rev	Log message	Author	Age	Path
12	pps sequence added to test bench endOfTx added to TxCore	acapola	4989d 10h	/iso7816_3_master/trunk/test/tbIso7816_3_Master.v
11	added BSD licence header to files	acapola	4989d 14h	/iso7816_3_master/trunk/test/tbIso7816_3_Master.v
10	communication direction probe added	acapola	4989d 15h	/iso7816_3_master/trunk/test/tbIso7816_3_Master.v
9	parity convention fixed	acapola	4995d 12h	/iso7816_3_master/trunk/test/tbIso7816_3_Master.v
8		acapola	4997d 10h	/iso7816_3_master/trunk/test/tbIso7816_3_Master.v
7	- rx/tx use "cyclesPerEtu" input - "stopBit" status bit timing fixed - analyzer: "lastByte" and "bytesCnt" functional	acapola	4998d 10h	/iso7816_3_master/trunk/test/tbIso7816_3_Master.v
6	analyzer added to test bench, not functional yet...	acapola	4999d 10h	/iso7816_3_master/trunk/test/tbIso7816_3_Master.v
4	Basic test bench completed for T=0: a card send ATR, reader send a command TODO: add cycles/ETU management (start at 372, then adjust in case of PPS...)	acapola	5001d 11h	/iso7816_3_master/trunk/test/tbIso7816_3_Master.v
3	initial draft, not functional yet	acapola	5008d 12h	/iso7816_3_master/trunk/test/tbIso7816_3_Master.v