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URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

[/] [iso7816_3_master/] [trunk/] [test/] [tbIso7816_3_Master.v] - Rev 17

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Rev	Log message	Author	Age	Path
15	tpdu level tasks inverse convention	acapola	5027d 13h	/iso7816_3_master/trunk/test/tbIso7816_3_Master.v
14	Task to send strings as bytes improved	acapola	5030d 13h	/iso7816_3_master/trunk/test/tbIso7816_3_Master.v
13	Corrections in analyzer to handle TDi and historical bytes in ATR and PPS todo: handle inverse convention	acapola	5031d 16h	/iso7816_3_master/trunk/test/tbIso7816_3_Master.v
12	pps sequence added to test bench endOfTx added to TxCore	acapola	5042d 12h	/iso7816_3_master/trunk/test/tbIso7816_3_Master.v
11	added BSD licence header to files	acapola	5042d 16h	/iso7816_3_master/trunk/test/tbIso7816_3_Master.v
10	communication direction probe added	acapola	5042d 18h	/iso7816_3_master/trunk/test/tbIso7816_3_Master.v
9	parity convention fixed	acapola	5048d 14h	/iso7816_3_master/trunk/test/tbIso7816_3_Master.v
8		acapola	5050d 12h	/iso7816_3_master/trunk/test/tbIso7816_3_Master.v
7	- rx/tx use "cyclesPerEtu" input - "stopBit" status bit timing fixed - analyzer: "lastByte" and "bytesCnt" functional	acapola	5051d 12h	/iso7816_3_master/trunk/test/tbIso7816_3_Master.v
6	analyzer added to test bench, not functional yet...	acapola	5052d 12h	/iso7816_3_master/trunk/test/tbIso7816_3_Master.v
4	Basic test bench completed for T=0: a card send ATR, reader send a command TODO: add cycles/ETU management (start at 372, then adjust in case of PPS...)	acapola	5054d 13h	/iso7816_3_master/trunk/test/tbIso7816_3_Master.v
3	initial draft, not functional yet	acapola	5061d 14h	/iso7816_3_master/trunk/test/tbIso7816_3_Master.v

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